1. Field of the Invention
The present invention generally relates to a bipolar transistor integrated circuit, and more particularly, it relates to an improvement in an electrode portion of a bipolar transistor in an integrated circuit.
2. Description of the Prior Art
In general, a bipolar transistor for an integrated circuit is formed in an island electrically isolated by a method such as p-n junction isolation, oxide film isolation or triple diffusion. Such a semiconductor device is disclosed in, e.g., U.S. Pat. No. 4,445,268 and U.S. patent application Ser. No. 698,523 filed Feb. 5, 1985. Further, formation of a self-aligned semiconductor device is disclosed in "Subnanosecond Self-Aligned I.sup.2 L/MTL Circuits", IEEE Transactions on Electron Device, Vol. ED-27, No. 8, August 1980, p. 1379.
FIGS. 1A to 1E are cross-sectional views showing principal steps of a conventional method of manufacturing a bipolar transistor in an integrated circuit. The conventional method is now described with reference to these drawings. An n.sup.+ -type layer 2 of high impurity concentration for implementing a buried collector layer is selectively formed on a p.sup.- -type silicon substrate 1 of low impurity concentration, followed by growth of an n.sup.- -type epitaxial layer 3 thereon (FIG. 1A).
Then the substance is selectively oxidized by utilizing a nitride mask film 201 on an under-layer oxide film 101, whereby a thick isolation oxide film 102 is formed while a p-type channel-cut layer 4 is simultaneously formed under the isolation oxide film 102 (FIG. 1B).
The nitride film 201 and the under-layer oxide film 101 are then removed to newly form an oxide film 103 for preventing ion channelling in the silicon crystal during ion implantation, thereby to form a p.sup.+ -type layer 5 for implementing an extrinsic base layer with a photoresist mask film (this mask film is not shown). Thereafter the photoresist film is removed to newly form a photoresist mask film 301 for forming a p-type layer 6 for implementing an active base layer by ion implantation (FIG. 1C).
The photoresist film 301 is then removed and the substance is covered by a passivation film 401 generally made of phospho-silicate glass (PSG). The substance is then subjected to heat treatment for annealing the ion implanted layers 5 and 6 to form an extrinsic base layer 51 and an active base layer 61 at an intermediate stage as well as densificating the PSG film 401, followed by formation of holes 70 and 80 in the PSG film 401 to form an n.sup.+ -type layer 7 for implementing an emitter layer and an n.sup.+ -type layer 8 for implementing a low resistance layer underneath a collector electrode by ion implantation (FIG. 1D).
Thereafter the respective ion implanted layers are annealed to completely implement an extrinsic base layer 52 and an active base layer 62 and to form an emitter layer 71 and a low resistance layer 81, followed by formation of hole 50 for a base electrode. Then the respective holes 50, 70 and 80 are provided with films 501 of metal silicide such as platinum silicide (Pt-Si) and palladium silicide (Pd-Si) for preventing junction-spike of the electrodes, followed by formation of a base electrode wire 9, an emitter electrode wire 10 and a collector electrode wire 11 by low-resistance metal such as aluminum (Al) (FIG. 1E).
FIG. 2 is a plan view showing a pattern of single-base structure which corresponds to FIG. 1E.
Generally, the frequency characteristic of a transistor depends on the base-collector capacitance and the base resistance, both of which must be decreased for improving the frequency characteristic. The p.sup.+ -type extrinsic base layer 52 is provided for lowering the base resistance in the aforementioned structure, whereas the provision of the same leads to an increase in the base-collector capacitance. In FIG. 2, an inactive base area between an emitter area 71 and an isolation oxide film boundary A also increases the base-collector capacitance. Thus, the emitter area 71 may be bounded by the isolation oxide film to be in walled a emitter structure. However, such a method involves various disadvantages as will be seen from FIGS. 3A to 3C.
FIGS. 3A to 3C are partial enlarged sectional views taken along the line X--X in FIG. 2. In FIG. 3A, boron is injected with a photoresist mask film 301 to form a base layer. Then, etching of the walled emitter structure is enhanced at the boundary of an isolation oxide film 102 as indicated by symbol A in FIG. 3B, and thus the emitter layer 71 is locally deepened as shown at B in FIG. 3C. Thus, lowered is controllability of the current amplification factor and increased is possibility of emitter-collector short circuit at the point B in FIG. 3C. Further, as shown in FIG. 2, the base resistance depends on a separation D.sub.1 between the emitter area 71 and the base electrode 501 (hole 50), i.e., the separation between the base wire 9 and the emitter wire 10 plus the total width of mrrgins of the respective wires 9 and 10 extending beyond the respective width of holes 50 and 70, and such margins inevitably remain even if the distance between the electrode wires 9 and 10 is reduced by improving accuracy of photoetching.
The transistor may also be brought in the double-base structure as shown in FIG. 4 for reducing the base resistance, as well known in the art. However, the increased base area of the double-base structure results in increasing of the base-collector capacitance.